Accurate definitions for setup and hold times in flip-flops, latch circuits and the like (hereinafter, “flop elements”) are crucial in state of the art integrated circuit design and fabrication. Setup time generally refers to the minimum amount of time that a data signal entering a flip flop must be stable before a clock edge; and hold time refers to the minimum amount of time that the data signal must be stable after the clock edge. Setup and hold times are defined to reliably sample the data signal and avoid metastability.
With increasing variation among fabrication processes, traditional setup and hold time definitions for flop elements are becoming outdated and impractical. The conventional setup and hold time definitions rely on a factor of 10% of the push out of clock-to-q delay as shown in FIGS. 1A-B. This conventional definition inherently assumes that all transistors on a chip are equally fast, which is not a practical assumption. The conventional definition also ignores the effect of circuit topologies, which in fact affect setup and hold times of individual flop elements. Another problem with the conventional definition is that it ignores the differences in setup and hold time requirements in scan/test mode and normal operation. Scan tests are typically performed at low speed and 10% push out of clock-to-q is insufficient to cause failures and accurately test the flop elements.
Existing approaches for overcoming the above problems with conventional 10% push-out of clock-to-q definitions include, monitoring a voltage at an internal node of associated with the setup and hold. The approach assumes that once the monitored voltage reaches a predetermined threshold, such as 15% of supply voltage (Vdd), the data signal sampled by the flop element may become unstable. Setup and hold times are defined based on the times taken to reach the predetermined threshold. However, if the predetermined threshold is set too low, such as 10% of Vdd, the circuits are rendered excessively sensitive to noise and crosstalk; and if the predetermined threshold is set too high, then low Vdd circuits are adversely impacted.
Another approach to overcome the problems with the 10% push-out of clock-to-g definitions includes defining setup and hold times based on an internal latch node voltage glitch level. This approach attempts to account for setup and hold time dependencies on circuit topology. However, this approach also is voltage dependent and does not work well for low Vdd circuits.
In addition to aforementioned drawbacks, the current approaches for characterizing setup and hold time requirements, suffer from another serious drawback, in that they ignore the importance of yield on the setup and hold time definitions. In general, yield refers to a percentage of circuit elements which perform properly once a chip is fabricated, and is a function of the number of circuits integrated on a chip. It is observed that the setup and hold times required for a chip with fewer flop elements is lower than the setup and hold time requirements for a chip with millions of flop elements. Accordingly, yield must be accounted for in setup and hold time definitions.
Therefore there is a need in the art for setup and hold time definitions which overcome drawbacks of current approaches, while faithfully accounting for process variations and yield based dependencies.